The present invention is related to a method for manufacturing a semiconductor device.
In semiconductor device manufacturing, for minimizing the size of a semiconductor device, a metal gate electrode (or metal gate) may be used instead of a traditional polysilicon gate electrode (or polysilicon gate). The metal gate may prevent issues related to polysilicon gate depletion and may minimize a threshold voltage associated with the semiconductor device.
Typically, a metal gate may be implemented using one of the following methods: a high-k first, metal-gate first method; a high-k first, metal-gate last method; and a high-k last, metal-gate last method. For manufacturing a complementary metal-oxide-semiconductor (CMOS) device with substantially small feature sizes, e.g., less than 20 nm, a high-k last, metal-gate last method may be used.
In order for a CMOS device with small feature sizes to meet performance requirements, the associated equivalent oxide thickness (EOT) may be substantially small. For attaining a small EOT without exposing the metal gate, a high-k material and a gate oxide layer may be combined to function as a gate dielectric layer.
In a high-k last, metal-gate process, a high-k dielectric layer and a high-k cap may be formed through deposition after a gate trench for accommodating a metal gate has been formed. This arrangement may substantially complicate the formation of the gate stack, especially for manufacturing a semiconductor device with feature sizes less than 20 nm.
In addition, in a high-k last, metal-gate process, an NMOS (N-channel metal-oxide-semiconductor field-effect transistor) and a PMOS (N-channel metal-oxide-semiconductor field-effect transistor) may be manufactured at the same time. In the process, implementation of a dual work function metal gate to satisfy work function requirements associated with both the PMOS and NMOS may be substantially difficult.
If the gate stack structure at the NMOS region and the gate stack structure at the PMOS region are manufactured at the same time, the EOT thickness at the NMOS region and the EOT thickness at the PMOS region may not be differently configured and optimized, such that the performance of the semiconductor device may not be optimal.
If the NMOS gate stack and the PMOS gate stack are manufactured separately according to well-known processes, unwanted residual high-k material may remain at contact interfaces of metal gates in the semiconductor device, resulting in undesirable high gate resistance.